Bài tập Thiết kế luận lý 1 - Chương 5: Flip Flop - Nguyễn Quang Huy
dce 5.1
2011
• Assuming that Q = 0 initially, apply the x and y
waveforms to SET and CLEAR inputs of a NAND
latch, determine the Q and Q’
Exercise Chapter 5 - Flip Flop
2
dce 5.2
2011
• Invert x and y waveforms, apply to SET and
CLEAR inputs of a NOR latch, determine Q and
Q’, assume Q = 0 initially
Exercise Chapter 5 - Flip Flop
3
dce 5.3
2011
• Q = 0 initially, determine Q waveform
Exercise Chapter 5 - Flip Flop
4
dce 5.4
2011
• Modify the circuit to use a NOR gate latch
Exercise Chapter 5 - Flip Flop
5
dce 5.5
2011
• Modify the circuit (Figure 5.12) to use a NAND
gate latch
Exercise Chapter 5 - Flip Flop
6
dce 5.9
2011
• Apply the waveforms to FF in Figure 5-17, 5-18.
Assume Q = 0 initially
Exercise Chapter 5 - Flip Flop
7
dce 5.11
2011
• Apply a 10-kHz clock signal to CLK of a J-K FF
that has J = K = 1. Determine the waveform at Q.
• Connect Q this FF to CLK of a 2nd J-K FF that
also has J = K = 1. Determine the frequency of
the signal at this FF’s output.
Exercise Chapter 5 - Flip Flop
8
dce 5.12
2011
• Positive/Negative-edge-triggered J-K
Exercise Chapter 5 - Flip Flop
9
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