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Bài giảng CUDA programming basic - Dương Nhật Tân

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High Performance Computing Center  
Hanoi University of Science & Technology  
CUDA Programming Basic  
Duong Nhat Tan ([email protected])  
2012  
Outline  
CUDA Installation  
Kernel launches  
Some specifics of GPU code  
High Performance Computing Center  
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Design Goals  
Scale to 100’s of cores, 1000’s of parallel threads  
G80  
GT200  
Tesla  
Fermi  
+
NVIDIA CUDA  
Let programmers focus on parallel algorithms  
Enable heterogeneous systems (i.e., CPU+GPU)  
CPU & GPU are separate devices with separate DRAM  
High Performance Computing Center  
3
GPU Computing with CUDA  
CUDA: Compute Unified Device Architect  
Application Development Environment for NVIDIA GPU  
Compiler, debugger, profiler, high-level programming languages  
Libraries (CUBLAS, CUFFT, ..) and Code Samples  
CUDA C languages  
The extension of C/C++  
Data parallel programming  
Executing a thousands of processes in  
parallel on GPUs  
Cost of synchronization is not expensive  
CUDA Installation  
CUDA development tools consists of three  
key components:  
CUDA driver  
CUDA toolkit  
Compiler, Assembler  
Libraries  
Documentation  
CUDA SDK  
http://developer.nvidia.com/category/zone/cuda-zone  
High Performance Computing Center  
5
CUDA SDK  
High Performance Computing Center  
6
CUDA files  
Routines that call the device must be in plain C –  
with extension .cu  
Often 2 files  
1) The kernel -- .cu file containing routines that are  
running on the device.  
2) A .cu file that calls the routines from kernel. includes the  
kernel  
Optional additional .cpp or .c files with other  
routines can be linked  
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Compilation  
Any source file containing CUDA language  
extensions must be compiled with NVCC  
NVCC is a compiler driver  
Works by invoking all the necessary tools and compilers like gcc,  
g++, cl, ...  
NVCC outputs:  
C code (host CPU Code)
‏
 
PTX  
8
Compilation  
High Performance Computing Center  
9
Conceptual Foundations  
Kernels: C functions, when called, are  
executed by many CUDA threads  
Threads  
Each thread has a unique thread ID  
Threads can be 1D, 2D, or 3D  
Thread id is accessible within the kernel using  
threadIdx variable  
Blocks  
A group of threads (1D, 2D, 3D)  
Block id is accessible within the kernel using  
blockIdx variable  
Grids  
A group of blocks  
Define the total number of threads (N) can be  
executed in parallel  
Threads in different block in the same grid cannot  
directly communicate with each other  
High Performance Computing Center  
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CUDA C kernel  
kernel<<<numBlocks,ThreadsPerBlock>>>(…parameter list …);  
// Kernel definition  
// function definition  
__global__ void VecAdd( float * A,  
void VecAdd( float * A, float * B, float  
float * B, float * C)  
* C)  
{
{
int i = threadIdx.x;  
for (int i=0;i<N ; i++)  
C[i] = A[i] + B[i];  
}
C[i] = A[i] + B[i];  
}
int main()  
int main()  
{
{
...  
...  
// Kernel invocation  
//function invocation  
VecAdd<<<1, N>>>(A, B, C);  
}
VecAdd(A, B, C);  
}
Data Parallelism  
A CUDA kernel is executed by an array of  
threads  
All threads run the same code  
Each thread has an ID that it uses to compute  
memory addresses and make control decisions  
12  
CUDA kernel and thread  
Parallel portions of an application are executed on  
the device as kernels  
One kernel is executed at a time  
Many threads execute each kernel  
Differences between CUDA and CPU threads  
CUDA threads are extremely lightweight  
Very little creation overhead  
Instant switching  
CUDA uses 1000s of threads to achieve efficiency  
Multi-core CPUs can use only a few  
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Kernel Memory Access  
Registers  
Global Memory  
Kernel input and output data reside  
here  
Off-chip, large  
Uncached  
Shared Memory  
Shared among threads in a single  
block  
On-chip, small  
As fast as registers  
The host can read & write global  
memory but not shared memory  
High Performance Computing Center  
14  
Hetegenerous Programming  
High Performance Computing Center  
15  
Execution Model  
Single Instruction Multiple Thread (SIMT) Execution:  
•
Groups of 32 threads formed  
into warps  
o always executing same instruction  
o share instruction fetch/dispatch  
o hardware automatically handles divergence  
•
Warps are primitive unit of scheduling  
High Performance Computing Center  
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Execution Model  
High Performance Computing Center  
17  
GPU Memory Allocation / Release  
cudaMalloc(void ** pointer, size_t nbytes)  
cudaMemset(void * pointer, int value, size_t count)  
cudaFree(void* pointer)  
int n = 1024;  
int nbytes = 1024*sizeof(int);  
int *d_a = 0;  
cudaMalloc( (void**)&d_a, nbytes );  
cudaMemset( d_a, 0, nbytes);  
cudaFree(d_a);  
High Performance Computing Center  
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Data copies  
cudaMemcpy(void *dst, void *src, size_t nbytes,  
enum cudaMemcpyKind direction);  
Direction specifies locations (host or device) of src and dst  
Blocks CPU thread: returns after the copy is complete  
Doesn’t start copying until previous CUDA calls complete  
enum cudaMemcpyKind  
cudaMemcpyHostToDevice  
cudaMemcpyDeviceToHost  
cudaMemcpyDeviceToDevice  
High Performance Computing Center  
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Copying between host  
and device  
Part1: Allocate memory for pointers d_a and d_b on  
the device.  
Part2: Copy h_a on the host to d_a on the device.  
Part3: Do a device to device copy from d_a to d_b.  
Part4: Copy d_b on the device back to h_a on the  
host.  
Part5: Free d_a and d_b on the host  
High Performance Computing Center  
20  
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